Languages, Design Methods, and Tools for Electronic System Design by Franco Fummi & Robert Wille

Author:Franco Fummi & Robert Wille
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

5.3 Testbench

This section provides more details on the testbench focusing on assertion generation to guide the formal analysis. For illustration purpose, we discuss a (simplified) concrete example testbench for the IRQMP. Essentially, the input specifies incoming interrupts for the IRQMP and the output is a prioritized list of interrupt requests generated by the IRQMP.

When sending the interrupt mask 0b110 as input and injecting a fault in the RTL model that results in wrong prioritization, the output [2, 3] is observed instead of the expected output [3, 2]—since higher interrupt lines have higher priority. Based on the input and faulty output the testbench is constructed. The monitoring logic records the observed interrupts in an array irq. Furthermore, it keeps track of the number of received interrupts in the num_irqs variable. Finally, the monitor asserts that ((irq[0] ≠ 2) | | (irq[1] ≠ 3) | | (num_irqs ≠ 2)) holds at the end of simulation. Essentially, it asserts that the observed output for the TLM model is not equal to the output of the faulty RTL model. Thus, the symbolic simulation engine will search for all possible error inject locations that violate the assertion, i.e., produce the same failure at TLM as the faulty RTL model.

As an optimization, to prune irrelevant search paths which cannot produce the output of the faulty RTL model, we place assume instructions in the monitor. For this example, we would assume that the first received interrupt is 2 and the second is 3. Furthermore, we would assume that num_irqs < 2. Then a simple assert (false); can be placed at the end of simulation. Using stepwise assumptions during symbolic simulation, instead of a single assert in the end, can significantly reduce the considered search space, by pruning irrelevant search paths early.

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